This invention relates to methods of manufacturing a semiconductor device, more particularly methods which preclude the formation of crystallographic faults in highly microminiaturized integrated circuit semiconductor devices.
In the semiconductor technology higher performance and lower cost per device are achieved by reducing the size of the active and passive semiconductor elements and by reducing the vertical thickness of the portion of the semiconductor wafer which contain the active and passive devices. The cost per device is reduced since many more devices can be fabricated from a single semiconductor wafer using a given sequence of process steps when the devices are made smaller. The total cost of the process steps and materials can then be divided by a larger number of devices. The reduced size of the devices also increases performance since the parasitic capacitive and inductive characteristics are reduced.
As integrated circuit semiconductor device structure becomes more dense, the inadvertent overlapping of opposite type highly doped impurity regions becomes more frequent. An example of a typical device application wherein adjacent highly doped opposite type conductivity regions are likely to overlap is shown in FIG. 1. FIG. 1 illustrates a transistor 10 as described in commonly assigned application SN 150,609, filed June 7, 1971, having an emitter region 12, a base region 14, a subcollector region 16, and a reach through collector contact 18. Transistor 10 is electrically isolated from adjacent elements on the common substrate 20 by a ring of recessed oxide 22 which surrounds the transistor. Beneath oxide 22 is provided a highly doped subisolation region 24 which bridges the distance in the epitaxial layer 21 between the bottom of region 22 and the substrate 20. The P-N junction between the subcollector region 16 and substrate 20 completes the electrical isolation of transistor 10. As the density of the devices gets greater, the probability of regions 16 and 24 overlapping becomes greater. Should regions 16 and 24 overlap, and the regions are heavily doped, it has been observed that crystallographic faults form in the overlapped region which emanate in all directions. These crystallographic faults cause leaks and/or shorts between the various regions of the transistor and also between the transistor and adjacent elements on the semiconductor substrate 20.